HiGame

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As the pace of Moore’s Law has slowed and shifted, every process node has become more difficult and complicated to achieve. The old days, where a simple die shrink automatically brought faster chips and lower power consumption, are now gone. Today, companies perform a die shrink (which makes most aspects of the chip perform worse, not better), and then find supplementary technologies that can improve performance and bring yields and power consumption back to full. Analyst and RealWorldTech owner David Kanter has published a paper on where he thinks Intel is headed at the 10nm node, and predicts the tech giant will deploy a pair of new technologies at that node — quantum well FETs and III-V semiconductors.

We’ve talked about III-V semiconductors first, so we’ll start there. Intel has been evaluating next-generation semiconductor materials for years. We first spoke with Mark Bohr about the company’s efforts back in 2012. The III-V semiconductors are called that because the materials are drawn from Groups III and V of the periodic table. Many of these materials have superior performance compared with silicon — either they use less power or they allow for drastically higher clock speeds. But they cost more and often require extremely sophisticated manufacturing techniques. Finding materials to replace both the p-channel and n-channel has been difficult, since some of the compounds used for one type of structure don’t work well for the other.
Kanter predicts that Intel will use either InGaAs (Indium Gallium Arsenide) or InSb (indium tin) for n-type, and strained germanium or additional III-V materials for the p-type channel. The net effect of this adoption could cut operating voltages as far as 0.5v. This is critical to further reducing idle and low-use power consumption, because power consumption today rises as the square or cube of voltage increase (depending on leakage characteristics and overall transistor type).

The other major advantage that Kanter thinks Intel may deploy is the use of quantum well structures. Quantum wells trap electrons by surrounding them with an insulating structure that leaves a limited number of dimensions for the electrons to move in. This new fin structure and gate are shown in the image below, from an Intel IEDM paper in 2011.




Combined, these new structures would allow Intel to substantially cut power consumption while simultaneously improving other characteristics of the transistor’s performance. It’s not clear if this would enable substantially faster chips. Intel has focused primarily on making its CPUs more efficient in the past five years, as opposed to making them faster. And while a Core i7-4790K is unquestionably quicker than a Core i7-2600K from 2010, the gap isn’t what it would’ve been ten years ago.

It’s possible that these new structures would run at substantially higher clock speeds. But building chips smaller also means decreasing feature sizes, which increases the formation of hot spots on the die. The ability to run chips at 0.5v is great for the Internet of Things, but it’s not necessarily great if the chip needs 1.1V to hit maximum clock.

Uncertainty at 10nm and below

Kanter addresses why he wrote this piece, noting he believes that “industry experts should make insightful, specific, verifiable predictions that have a definite time horizon.” It makes sense that Intel would go for some of these capabilities. The firm is known to be researching III-Vs, and quantum wells have apparently been worked on for a decade or more. Intel likes to talk up its manufacturing capabilities and advantages, and this type of innovation at the 10nm node could give them a huge leg up over the competition.

Samsung and TSMC haven’t revealed much about their own plans, but it’s highly likely that both firms would stick with conventional FinFET designs at 10nm, just as Intel spent two design cycles using their own standard Tri-gate technology. If TSMC actually closes the gap with Intel at 10nm, III-Vs and QWFETs would give Intel an argument for claiming it’s not just the number of nanometers that makes the difference — it’s the process tech as well.

If Intel adopts these technologies at 10nm, it’ll push back the window on EUV farther, back to 7nm — and possibly require additional verification and validation that the tool sets are compatible with both the new semiconductor manufacturing equipment and the requirements of EUV itself. Such a move would likely push EUV introduction back into the 2018-2019 timeframe, assuming that 10nm shipments begin in 2016-2017, with 7nm ready 2-3 years later.

Intel supposedly delayed installation of 10nm equipment until December of this year, but is planning to ramp production at its facilities in Israel.


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